Development of MIPI Camera Interface Prototype Adapter Board

This project is the development of the prototype FPGA (Field Programmable Gate Array)-Compatible MIPI CSI-2 (Camera Serial Interface) D-PHY adapter board. The FPGA used on the SpaceCube processor card does not have I/O that natively supports the D-PHY standard, and thus requires additional external components to adapt the interface to the FPGAs I/O. The goal of this project is to develop a prototype board with this external circuitry. The project tasks include 1) preliminary research and analysis of the adapter circuit requirements involving waveform comparisons, 2) signal processing chain tests for voltage measurements, 3) calculations from I/O channel system simulations in TI-TINA, 4) components’ values and circuit configuration verifications, 5) protoboard schematic entry, 6) both PCB footprint builds and PCB layout in Altium Designer, and lastly, 7) PCB manufacturing. The project requires the applications of fundamental electrical engineering laws such as Ohm’s Law and Kirchhoff’s Voltage Law for calculations of components’ values and signal analysis concepts to build the architecture of the prototype PCB during the iterative development process. The completed PCB shows the 3 receiver networks with confirmed values from the circuit simulations and waveform analyses, the 2 connectors with I/O pin reconfigurations, and both the differential trace pairs and single traces between the components and connectors. The trace routes are subjected to Altium’s rules, which enable efficient use of routing parameters for signal integrity. This adapter board is useful in data conversion and transmission from the MIPI camera module to the FPGA, a D- PHY circuit arrangement used in NASA’s SpaceCube Mini’s VADIR (Versatile Analog/Digital Interface) between the MIPI Camera module and the Backplane Connector. Once the adapter board PCB is fabricated and assembled, it can be used to demonstrate the validity of the circuit design prior to it being incorporated into the VADIR flight board design

Modular Architecture for a Resilient Extensible SmallSat (MARES)

CubeSats and SmallSats have seen increasing success in Low Earth Orbit (LEO). However, there is a desire to send small, low cost missions beyond LEO into harsher environments. Additionally, most bus architectures do not currently have the on-board processing capa-bilities to handle high-speed science data and autonomous operations. MARES, currently under development at NASA’s Goddard Space Flight Center, is a capabilities driven design and architecture with an emphasis on reliability, scalability, and high performance process-ing. Its applicability is broad including SmallSat missions, CubeSat missions, and high performance instrument processors. The highly integrated architecture reduces mass, volume, and power but still provides the flexibility of a modular system. Mission critical functions are handled by the Command and Data Handling (C&DH) Processor and Auxiliary cards, which are radiation hardened up to 100krad. SpaceCube™ Mini 3 processor card is primarily used for instrument data processing but its versatility and processing power provides a digital platform to reduce the SWaP of components and applications such as above-the-constellation GPS, software defined radio and LIDAR. This can be achieved by utilizing the same Mini card for various applications but multiple units can be utilized on the same bus if needed via a backplane design for the bus avionics. The catalog of new cards and features for MARES continues to grow, and the architecture can be expanded further with the design of mission-specific cards that plug into the same backplane as the rest of the bus. Standardized backplane configurations will reduce resources spent on customization and ensure a robust and compatible system

NASA SpaceCube Edge TPU SmallSat Card for Autonomous Operations and Onboard Science-Data Analysis

Using state-of-the-art artificial intelligence (AI)frameworks onboard spacecraft is challenging because common spacecraft processors cannot provide comparable performance to data centers with server-grade CPUs and GPUs available for terrestrial applications and advanced deep-learning networks. This limitation makes small, low-power AI microchip architectures, such as the Google Coral Edge Tensor Processing Unit (TPU), attractive for space missions where the application-specific design enables both high-performance and power-efficient computing for AI applications. To address these challenging considerations for space deployment, this research introduces the design and capabilities of a CubeSat-sized Edge TPU-based co-processor card, known as the SpaceCube Low-power Edge Artificial Intelligence Resilient Node (SC-LEARN). This design conforms to NASA’s CubeSat Card Specification (CS2) for integration into next-generation SmallSat and CubeSat systems. This paper describes the overarching architecture and design of the SC-LEARN, as well as, the supporting test card designed for rapid prototyping and evaluation. The SC-LEARN was developed with three operational modes: (1) a high-performance parallel-processing mode,(2)a fault-tolerant mode for onboard resilience, and (3) a power-saving mode with cold spares. Importantly, this research also elaborates on both training and quantization of TensorFlow models for the SC-LEARN for use onboard with representative, open-source datasets. Lastly, we describe future research plans, including radiation-beam testing and flight demonstration

NASA SpaceCube Intelligent Multi-Purpose System for Enabling Remote Sensing, Communication, and Navigation in Mission Architectures

New, innovative CubeSat mission concepts demand modern capabilities such as artificial intelligence and autonomy, constellation coordination, fault mitigation, and robotic servicing – all of which require vastly more processing resources than legacy systems are capable of providing. Enabling these domains within a scalable, configurable processing architecture is advantageous because it also allows for the flexibility to address varying mission roles, such as a command and data-handling system, a high-performance application processor extension, a guidance and navigation solution, or an instrument/sensor interface. This paper describes the NASA SpaceCube Intelligent Multi-Purpose System (IMPS), which allows mission developers to mix-and-match 1U (10 cm × 10 cm) CubeSat payloads configured for mission-specific needs. The central enabling component of the system architecture to address these concerns is the SpaceCube v3.0 Mini Processor. This single-board computer features the 20nm Xilinx Kintex UltraScale FPGA combined with a radiation-hardened FPGA monitor, and extensive IO to integrate and interconnect varying cards within the system. To unify the re-usable designs within this architecture, the CubeSat Card Standard was developed to guide design of 1U cards. This standard defines pinout configurations, mechanical, and electrical specifications for 1U CubeSat cards, allowing the backplane and mechanical enclosure to be easily extended. NASA has developed several cards adhering to the standard (System-on-Chip, power card, etc.), which allows the flexibility to configure a payload from a common catalog of cards

Vu Villa Staircase Structural Repair

The Vu Villa in uptown Butte has a staircase leading to the second floor that is beginning to sag and needs structural support to fix the sag in the stairs

SpaceCube v3.0 NASA Next-Generation High-Performance Processor for Science Applications

Electronics for space systems must address several considerable challenges including achieving operational resiliency within the hazardous space environment and also meeting application performance needs while simultaneously managing size, weight, and power requirements. To drive the future revolution in space processing, onboard systems need to be more flexible, affordable, and robust. In order to provide a robust solution to a variety of missions and instruments, the Science Data Processing Branch at NASA Goddard Space Flight Center (GSFC)has pioneered a hybrid-processing approach that combines radiation-hardened and commercial components while emphasizing a novel architecture harmonizing the best capabilities of CPUs, DSPs, and FPGAs. This hybrid approach is realized through the SpaceCube family of processor cards that have extensive flight heritage on a variety of mission classes. The latest addition to the SpaceCube family, SpaceCube v3.0, will function as the next evolutionary step for upcoming missions, allow for prototyping of designs and software, and provide a flexible, mature architecture that is also ready to adopt the radiation-hardened High-Performance Spaceflight Computing (HPSC) chiplet when it is released. The research showcased in this paper describes the design methodology, analysis, and capabilities of the SpaceCube v3.0 SpaceVPX Lite (VITA 78.1) 3U-220mm form-factor processor card

Metabolic consequences of interleukin-6 challenge in developing neurons and astroglia

Abstract Background: Maternal immune activation and subsequent interleukin-6 (IL-6) induction disrupt normal brain development and predispose the offspring to developing autism and schizophrenia. While several proteins have been identified as having some link to these developmental disorders, their prevalence is still small and their causative role, if any, is not well understood. However, understanding the metabolic consequences of environmental predisposing factors could shed light on disorders such as autism and schizophrenia. Methods: To gain a better understanding of the metabolic consequences of IL-6 exposure on developing central nervous system (CNS) cells, we separately exposed developing neuron and astroglia cultures to IL-6 for 2 hours while collecting effluent from our gravity-fed microfluidic chambers. By coupling microfluidic technologies to ultra-performance liquid chromatography-ion mobility-mass spectrometry (UPLC-IM-MS), we were able to characterize the metabolic response of these CNS cells to a narrow window of IL-6 exposure. Results: Our results revealed that 1) the use of this technology, due to its superb media volume:cell volume ratio, is ideally suited for analysis of cell-type-specific exometabolome signatures; 2) developing neurons have low secretory activity at baseline, while astroglia show strong metabolic activity; 3) both neurons and astroglia respond to IL-6 exposure in a cell type-specific fashion; 4) the astroglial response to IL-6 stimulation is predominantly characterized by increased levels of metabolites, while neurons mostly depress their metabolic activity; and 5) disturbances in glycerophospholipid metabolism and tryptophan/kynurenine metabolite secretion are two putative mechanisms by which IL-6 affects the developing nervous system. Conclusions: Our findings are potentially critical for understanding the mechanism by which IL-6 disrupts brain function, and they provide information about the molecular cascade that links maternal immune activation to developmental brain disorders

NASA SpaceCube Next-Generation Artificial-Intelligence Computing for STP-H9-SCENIC on ISS

Recently, Artificial Intelligence (AI) and Machine Learning (ML) capabilities have seen an exponential increase in interest from academia and industry that can be a disruptive, transformative development for future missions. Specifically, AI/ML concepts for edge computing can be integrated into future missions for autonomous operation, constellation missions, and onboard data analysis. However, using commercial AI software frameworks onboard spacecraft is challenging because traditional radiation-hardened processors and common spacecraft processors cannot provide the necessary onboard processing capability to effectively deploy complex AI models. Advantageously, embedded AI microchips being developed for the mobile market demonstrate remarkable capability and follow similar size, weight, and power constraints that could be imposed on a space-based system. Unfortunately, many of these devices have not been qualified for use in space. Therefore, Space Test Program - Houston 9 - SpaceCube Edge-Node Intelligent Collaboration (STP-H9-SCENIC) will demonstrate inflight, cutting-edge AI applications on multiple space-based devices for next-generation onboard intelligence. SCENIC will characterize several embedded AI devices in a relevant space environment and will provide NASA and DoD with flight heritage data and lessons learned for developers seeking to enable AI/ML on future missions. Finally, SCENIC also includes new CubeSat form-factor GPS and SDR cards for guidance and navigation

Digital Forensics Range

The Digital Forensics Range was developed to serve as an online training for groups interested in computer forensics. This year\u27s team had the goal to expand upon last year, by adding a new forensics image, unity scenario, and additional AWS functionality. The team still wanted to continue with last year\u27s goals of keeping the training easily runnable, quickly deployable, and rapidly scalable through the use of the cloud. Adding to last year\u27s work, this year\u27s team hoped to further increase the educational value of the simulation with more practice, and the addition of feedback. The training is meant to be easily approachable, and beneficial to all levels of forensics knowledge